	.module timer80.c
	.area text(rom, con, rel)
	.dbfile D:\01.Projects\JKElectronics\ATMEGA\CoreModule\sw\examples\lib\timer80.c
	.dbfunc e timer80_rtc_enable _timer80_rtc_enable fV
	.even
_timer80_rtc_enable::
	.dbline -1
	.dbline 9
; 
; #include "hw_config.h"
; #include "timer.h"
; #include "timer80.h"
; 
; 
; 
; void timer80_rtc_enable(void)
; {
	.dbline 10
; 	sbi(ASSR, AS0);
	in R24,0x30
	ori R24,8
	out 0x30,R24
	.dbline -2
L3:
	.dbline 0 ; func end
	ret
	.dbend
	.dbfunc e timer80_rtc_disable _timer80_rtc_disable fV
	.even
_timer80_rtc_disable::
	.dbline -1
	.dbline 14
; }
; 
; void timer80_rtc_disable(void)
; {
	.dbline 15
; 	cbi(ASSR, AS0);
	in R24,0x30
	andi R24,247
	out 0x30,R24
	.dbline -2
L4:
	.dbline 0 ; func end
	ret
	.dbend
	.dbfunc e timer80_interrupt_oc_enable _timer80_interrupt_oc_enable fV
	.even
_timer80_interrupt_oc_enable::
	.dbline -1
	.dbline 19
; }
; 
; void timer80_interrupt_oc_enable(void)
; {
	.dbline 20
; 	sbi(TIMSK, OCIE0);
	in R24,0x37
	ori R24,2
	out 0x37,R24
	.dbline -2
L5:
	.dbline 0 ; func end
	ret
	.dbend
	.dbfunc e timer80_interrupt_oc_disable _timer80_interrupt_oc_disable fV
	.even
_timer80_interrupt_oc_disable::
	.dbline -1
	.dbline 24
; }
; 
; void timer80_interrupt_oc_disable(void)
; {
	.dbline 25
; 	cbi(TIMSK, OCIE0);
	in R24,0x37
	andi R24,253
	out 0x37,R24
	.dbline -2
L6:
	.dbline 0 ; func end
	ret
	.dbend
	.dbfunc e timer80_interrupt_ov_enable _timer80_interrupt_ov_enable fV
	.even
_timer80_interrupt_ov_enable::
	.dbline -1
	.dbline 29
; }
; 
; void timer80_interrupt_ov_enable(void)
; {
	.dbline 30
; 	sbi(TIMSK, TOIE0);
	in R24,0x37
	ori R24,1
	out 0x37,R24
	.dbline -2
L7:
	.dbline 0 ; func end
	ret
	.dbend
	.dbfunc e timer80_interrupt_ov_disable _timer80_interrupt_ov_disable fV
	.even
_timer80_interrupt_ov_disable::
	.dbline -1
	.dbline 34
; }
; 
; void timer80_interrupt_ov_disable(void)
; {
	.dbline 35
; 	cbi(TIMSK, TOIE0);
	in R24,0x37
	andi R24,254
	out 0x37,R24
	.dbline -2
L8:
	.dbline 0 ; func end
	ret
	.dbend
	.dbfunc e timer80_interrupt_ovf_clear _timer80_interrupt_ovf_clear fV
	.even
_timer80_interrupt_ovf_clear::
	.dbline -1
	.dbline 39
; }
; 
; void timer80_interrupt_ovf_clear(void)
; {
	.dbline 40
; 	cbi(TIFR, TOV0);
	in R24,0x36
	andi R24,254
	out 0x36,R24
	.dbline -2
L9:
	.dbline 0 ; func end
	ret
	.dbend
	.dbfunc e timer80_interrupt_ocf_clear _timer80_interrupt_ocf_clear fV
	.even
_timer80_interrupt_ocf_clear::
	.dbline -1
	.dbline 44
; }
; 
; void timer80_interrupt_ocf_clear(void)
; {
	.dbline 45
; 	cbi(TIFR, OCF0);
	in R24,0x36
	andi R24,253
	out 0x36,R24
	.dbline -2
L10:
	.dbline 0 ; func end
	ret
	.dbend
	.dbfunc e timer80_init _timer80_init fV
;          a_Clk -> y+2
;   a_ComOutMode -> R18
; a_WaveFormMode -> R16
	.even
_timer80_init::
	st -y,R20
	st -y,R21
	.dbline -1
	.dbline 49
; }
; 
; void timer80_init(byte a_WaveFormMode, byte a_ComOutMode, byte a_Clk)
; {
	.dbline 61
; 	/*-------------------------------------------------------------------
; 	   8-bit Timer/Counter Register Description
; 	   TCCR0 (Timer/Counter Control Register define)
; 	=====================================================================
; 	Bit 	7 	6 	5 	4 	3 	2 	1 	0
; 	FOC0 WGM00 COM01 COM00 WGM01 CS02 CS01 CS00 TCCR0
; 	Read/Write W R/W R/W R/W R/W R/W R/W R/W
; 	Initial Value 0 0 0 0 0 0 0 0
; 	-------------------------------------------------------------------*/
; 
; 	// Waveform Generation Mode Bit
; 	switch(a_WaveFormMode)
	mov R20,R16
	clr R21
	cpi R20,0
	cpc R20,R21
	breq L15
X0:
	cpi R20,1
	ldi R30,0
	cpc R21,R30
	breq L16
X1:
	cpi R20,2
	ldi R30,0
	cpc R21,R30
	breq L17
X2:
	cpi R20,3
	ldi R30,0
	cpc R21,R30
	breq L18
X3:
	xjmp L12
L15:
	.dbline 64
; 	{
; 		case WAVE_NOR:	 // Normal 
; 						cbi(TCCR0,WGM00);
	in R24,0x33
	andi R24,191
	out 0x33,R24
	.dbline 65
; 						cbi(TCCR0,WGM01);	
	in R24,0x33
	andi R24,247
	out 0x33,R24
	.dbline 66
; 						break;
	xjmp L13
L16:
	.dbline 69
; 							
; 		case WAVE_PWM: // PWM,Phase Correct
; 						sbi(TCCR0,WGM00);
	in R24,0x33
	ori R24,64
	out 0x33,R24
	.dbline 70
; 						cbi(TCCR0,WGM01);									
	in R24,0x33
	andi R24,247
	out 0x33,R24
	.dbline 71
; 						break;
	xjmp L13
L17:
	.dbline 74
; 
; 		case WAVE_CTC:	// CTC
; 						cbi(TCCR0,WGM00);
	in R24,0x33
	andi R24,191
	out 0x33,R24
	.dbline 75
; 						sbi(TCCR0,WGM01);							
	in R24,0x33
	ori R24,8
	out 0x33,R24
	.dbline 76
; 						break;
	xjmp L13
L18:
	.dbline 79
; 	
; 		case WAVE_FPWM:	// Fast PWM
; 						sbi(TCCR0,WGM00);
	in R24,0x33
	ori R24,64
	out 0x33,R24
	.dbline 80
; 						sbi(TCCR0,WGM01);	
	in R24,0x33
	ori R24,8
	out 0x33,R24
	.dbline 81
; 	                    break;
L12:
L13:
	.dbline 85
; }
; 
; 	//Compare Output Mode(Normal, CTC)
; 	switch(a_ComOutMode)
	mov R20,R18
	clr R21
	cpi R20,0
	cpc R20,R21
	breq L22
X4:
	cpi R20,1
	ldi R30,0
	cpc R21,R30
	breq L23
X5:
	cpi R20,2
	ldi R30,0
	cpc R21,R30
	breq L24
X6:
	cpi R20,3
	ldi R30,0
	cpc R21,R30
	breq L25
X7:
	xjmp L19
L22:
	.dbline 88
; {
; 		case OC_NORMAL:	 // Normal port operation, OC0 disconnected.
; 						cbi(TCCR0,COM00);
	in R24,0x33
	andi R24,239
	out 0x33,R24
	.dbline 89
; 						cbi(TCCR0,COM01);	
	in R24,0x33
	andi R24,223
	out 0x33,R24
	.dbline 90
; 						break;
	xjmp L20
L23:
	.dbline 93
; 	
; 		case OC_TOG: // Toggle OC0 on compare match
; 						sbi(TCCR0,COM00);
	in R24,0x33
	ori R24,16
	out 0x33,R24
	.dbline 94
; 						cbi(TCCR0,COM01);									
	in R24,0x33
	andi R24,223
	out 0x33,R24
	.dbline 95
; 						break;
	xjmp L20
L24:
	.dbline 98
; 	
; 		case OC_CLE:	// Clear OC0 on compare match
; 						cbi(TCCR0,COM00);
	in R24,0x33
	andi R24,239
	out 0x33,R24
	.dbline 99
; 						sbi(TCCR0,COM01);							
	in R24,0x33
	ori R24,32
	out 0x33,R24
	.dbline 100
; 						break;
	xjmp L20
L25:
	.dbline 103
; 
; 		case OC_SET:	// Set OC0 on compare match
; 						sbi(TCCR0,COM00);
	in R24,0x33
	ori R24,16
	out 0x33,R24
	.dbline 104
; 						sbi(TCCR0,COM01);	
	in R24,0x33
	ori R24,32
	out 0x33,R24
	.dbline 105
; 	                    break;
L19:
L20:
	.dbline 109
; 	}
; 	
;     // CS02:0: Clock Select
; 	switch(a_Clk)
	ldd R20,y+2
	clr R21
	cpi R20,0
	cpc R20,R21
	breq L29
X8:
	cpi R20,1
	ldi R30,0
	cpc R21,R30
	breq L30
X9:
	cpi R20,2
	ldi R30,0
	cpc R21,R30
	breq L31
X10:
	cpi R20,3
	ldi R30,0
	cpc R21,R30
	breq L32
X11:
	cpi R20,5
	ldi R30,0
	cpc R21,R30
	brne X16
	xjmp L33
X16:
X12:
	cpi R20,6
	ldi R30,0
	cpc R21,R30
	brne X17
	xjmp L34
X17:
X13:
	cpi R20,10
	ldi R30,0
	cpc R21,R30
	brne X18
	xjmp L35
X18:
X14:
	cpi R20,11
	ldi R30,0
	cpc R21,R30
	brne X19
	xjmp L36
X19:
X15:
	xjmp L26
L29:
	.dbline 112
; 	{
; 		case CLK_STOP:	 // No clock source (Timer/Counter stopped).
; 						cbi(TCCR0,CS00);
	in R24,0x33
	andi R24,254
	out 0x33,R24
	.dbline 113
; 						cbi(TCCR0,CS01);
	in R24,0x33
	andi R24,253
	out 0x33,R24
	.dbline 114
; 						cbi(TCCR0,CS02);
	in R24,0x33
	andi R24,251
	out 0x33,R24
	.dbline 115
; 						break;
	xjmp L27
L30:
	.dbline 118
; 
; 		case CLK_NO:    // clkI/O/(No prescaling)
; 						sbi(TCCR0,CS00);
	in R24,0x33
	ori R24,1
	out 0x33,R24
	.dbline 119
; 						cbi(TCCR0,CS01);
	in R24,0x33
	andi R24,253
	out 0x33,R24
	.dbline 120
; 						cbi(TCCR0,CS02);									
	in R24,0x33
	andi R24,251
	out 0x33,R24
	.dbline 121
; 						break;
	xjmp L27
L31:
	.dbline 124
; 
; 		case CLK_8:	    // clkI/O/8 (From prescaler)
; 						cbi(TCCR0,CS00);
	in R24,0x33
	andi R24,254
	out 0x33,R24
	.dbline 125
; 						sbi(TCCR0,CS01);
	in R24,0x33
	ori R24,2
	out 0x33,R24
	.dbline 126
; 						cbi(TCCR0,CS02);							
	in R24,0x33
	andi R24,251
	out 0x33,R24
	.dbline 127
; 						break;
	xjmp L27
L32:
	.dbline 130
; 	
; 		case CLK_64:	// clkI/O/64 (From prescaler)
; 						sbi(TCCR0,CS00);
	in R24,0x33
	ori R24,1
	out 0x33,R24
	.dbline 131
; 						sbi(TCCR0,CS01);
	in R24,0x33
	ori R24,2
	out 0x33,R24
	.dbline 132
; 						cbi(TCCR0,CS02);	
	in R24,0x33
	andi R24,251
	out 0x33,R24
	.dbline 133
; 	                    break;
	xjmp L27
L33:
	.dbline 135
; 	    case CLK_256:	// clkI/O/256 (From prescaler)
; 						cbi(TCCR0,CS00);
	in R24,0x33
	andi R24,254
	out 0x33,R24
	.dbline 136
; 						cbi(TCCR0,CS01);
	in R24,0x33
	andi R24,253
	out 0x33,R24
	.dbline 137
; 						sbi(TCCR0,CS02);	
	in R24,0x33
	ori R24,4
	out 0x33,R24
	.dbline 138
; 						break;
	xjmp L27
L34:
	.dbline 141
; 
; 		case CLK_1024:  // clkI/O/1024 (From prescaler)
; 						sbi(TCCR0,CS00);
	in R24,0x33
	ori R24,1
	out 0x33,R24
	.dbline 142
; 						cbi(TCCR0,CS01);
	in R24,0x33
	andi R24,253
	out 0x33,R24
	.dbline 143
; 						sbi(TCCR0,CS02);									
	in R24,0x33
	ori R24,4
	out 0x33,R24
	.dbline 144
; 						break;
	xjmp L27
L35:
	.dbline 147
; 	
; 		case CLK_EXT_F:	// External clock source on T0 pin. Clock on falling edge.
; 						cbi(TCCR0,CS00);
	in R24,0x33
	andi R24,254
	out 0x33,R24
	.dbline 148
; 						sbi(TCCR0,CS01);
	in R24,0x33
	ori R24,2
	out 0x33,R24
	.dbline 149
; 						sbi(TCCR0,CS02);							
	in R24,0x33
	ori R24,4
	out 0x33,R24
	.dbline 150
; 						break;
	xjmp L27
L36:
	.dbline 153
; 	
; 		case CLK_EXT_R:	// External clock source on T0 pin. Clock on rising edge.
; 						sbi(TCCR0,CS00);
	in R24,0x33
	ori R24,1
	out 0x33,R24
	.dbline 154
; 						sbi(TCCR0,CS01);
	in R24,0x33
	ori R24,2
	out 0x33,R24
	.dbline 155
; 						sbi(TCCR0,CS02);	
	in R24,0x33
	ori R24,4
	out 0x33,R24
	.dbline 156
; 	                    break;
L26:
L27:
	.dbline -2
L11:
	.dbline 0 ; func end
	ld R21,y+
	ld R20,y+
	ret
	.dbsym l a_Clk 2 c
	.dbsym r a_ComOutMode 18 c
	.dbsym r a_WaveFormMode 16 c
	.dbend
; 	}
; 
; }
